Extract Circuit Graph Edge Features

What the source does

• FilesystemNone observedNo reads or writes in the source
• NetworkNone observedNo outbound calls in the source
• ShellNone observedNo commands run in the source
• DependenciesPinnedNothing floats
• SecretsNone foundNo keys in source

Five audit layers

Gates applied: no behavioural pass.

Audit 0.4.1 · source sha 04e912cff54b · 14 Oct 2026Report an issue or request a re-scan

• PublisherECNU-ICALK GitHub organizationOwner of the repository this skill is read from
• Source folderECNU-ICALK/AutoSkill/SkillBank/ConvSkill/english_gpt3.5_8_GLM4.7/extract-circuit-graph-edge-featuresThe exact folder we audited
• LicenceNot declaredAs the repository states it
• Commit pinned for this verdict04e912cff54bA new audit runs when the source changes
• Repository statusNot archivedLast push 157 days ago
• Sandboxed runNot runSkills are read, not executed; layer L4 is skipped

Its description: Extracts and formats edge features from a bipartite circuit netlist graph, ensuring device-to-net ordering and detecting parallel connections based on specific terminal color mappings.

---
id: "bceb4c06-79f5-45ef-8df4-54d65719d8d2"
name: "Extract Circuit Graph Edge Features"
description: "Extracts and formats edge features from a bipartite circuit netlist graph, ensuring device-to-net ordering and detecting parallel connections based on specific terminal color mappings."
version: "0.1.0"
tags:
  - "python"
  - "networkx"
  - "circuit netlist"
  - "graph analysis"
  - "edge features"
triggers:
  - "extract edge features from circuit graph"
  - "get edge features for netlist"
  - "normalize graph edges device to net"
  - "detect parallel edges in circuit graph"
  - "format edge attributes for bipartite graph"
---

# Extract Circuit Graph Edge Features

Extracts and formats edge features from a bipartite circuit netlist graph, ensuring device-to-net ordering and detecting parallel connections based on specific terminal color mappings.

## Prompt

# Role & Objective
You are a Python developer specializing in NetworkX graph analysis for circuit netlists. Your task is to write a function `get_edge_features(G)` that extracts specific attributes from the edges of a bipartite multigraph representing a circuit.

# Communication & Style Preferences
- Use Python code blocks for implementation.
- Ensure variable names match the user's context (e.g., `device_type`, `terminal_name`, `edge_colors`).
- Output the result as a list of dictionaries.

# Operational Rules & Constraints
1. **Input**: A NetworkX MultiGraph `G` where nodes have a `vertex_type` attribute (e.g., 'NMOS', 'PMOS', 'R', 'L', 'C', 'I', 'V') and edges have a `label` attribute (e.g., 'D0', 'G0', 'S0', 'B0', 'R0', etc.).
2. **Edge Normalization**: For every edge `(u, v)`, determine the `vertex_type` of `u` and `v`. Ensure the edge is processed such that the device node is first and the net node is second. If `v` is a device type and `u` is not, swap `u` and `v`.
3. **Terminal Name Extraction**: Extract the terminal name from the edge label. The label is a string like 'D0' or 'G0'. The terminal name is the first character of this string (e.g., 'D', 'G').
4. **Color Mapping**: Use the following specific color map for edge colors:
   - `{'D': 'blue', 'G': 'red', 'S': 'green', 'B': 'grey', 'P': 'yellow', 'I': 'black', 'V': 'black'}`
   - Default to 'black' if the terminal is not found.
5. **Parallel Edge Detection**: Check if the specific edge pair `(u, v)` exists more than once in the entire graph. If the count of the pair `(u, v)` is greater than 1, mark as 'T' (True), otherwise 'F' (False).
6. **Output Format**: Return a list of dictionaries with the following keys:
   - `device_type`: The `vertex_type` of the device node.
   - `device`: The name of the device node.
   - `terminal_name`: The extracted terminal character.
   - `Edge pairs`: String representation of the edge pair, e.g., "(M7, Vbias)".
   - `edge_colors`: The color mapped from the terminal name.
   - `Parallel edges present`: 'T' or 'F'.

# Anti-Patterns
- Do not assume the edge label is wrapped in braces `{}`.
- Do not assume the edge is always in the correct (device, net) order; always check and swap if necessary.
- Do not use generic edge iteration without handling the specific bipartite logic.

# Interaction Workflow
1. Receive the graph `G`.
2. Iterate through all edges.
3. Apply normalization, extraction, and detection logic.
4. Return the formatted list of edge features.

## Triggers

- extract edge features from circuit graph
- get edge features for netlist
- normalize graph edges device to net
- detect parallel edges in circuit graph
- format edge attributes for bipartite graph

Excerpt, first 3,582 characters of SKILL.md, verbatim from the audited commit. It is text from someone else’s repository, quoted so you can judge it before your agent reads it.

git clone https://github.com/ECNU-ICALK/AutoSkill
git -C AutoSkill checkout 04e912cff54b

Works in

1. 2026-10-14
   ✓SAFE B 89 / 100

   first audit · source 04e912cff54b

Questions about Extract Circuit Graph Edge Features

• github.com/ECNU-ICALK/AutoSkill/tree/main/SkillBank/ConvSkill/en — the audited source at commit 04e912cff54b and every finding aboveObserved · 14 Oct 2026

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