Matlab Analyze Pcb PdnSAFE

The MATLAB Agentic Toolkit brings proven MATLAB capabilities to AI agents, making engineering and scientific workflows agent-ready.

The instruction file, verbatim from the audited commit — this is the text the model reads, and the surface the audit's instruction layer examines. Quoted here so you can judge it without cloning anything.

---
name: matlab-analyze-pcb-pdn
description: "PDN DC voltage/current analysis, IR drop, design rule checking, and multi-net batch analysis on imported PCB layouts. TRIGGER: user asks about power integrity, PDN analysis, IR drop, voltage distribution, current density, power nets, or design rule checking on a PCB. Invoke BEFORE writing code — the PDN API chain is specialized and non-obvious. SKIP: importing a PCB file (use matlab-read-pcb-layout), EM field/S-parameter extraction (use matlab-analyze-em), material/stackup setup only (use matlab-manage-pcb-material), transmission line design (use matlab-design-pcb-transmission-line)."
license: https://www.mathworks.com/content/dam/mathworks/license/pmrl/license.md
metadata:
  author: MathWorks
  version: "1.0"
---

# Analyzing Power Distribution Networks (PDN)

## When to Use

- Analyzing DC voltage and current distribution on PCB power rails
- Checking design rules (max current density, voltage margins, via current limits)
- Discovering and listing power nets on an imported PCB layout
- Assigning source/load/sense topology for PDN analysis
- Running batch analysis across multiple power rails on a board
- Inferring nominal voltage from standard PCB net naming conventions

## When NOT to Use

- Importing PCB layouts (Gerber, ODB++, Allegro) — use `matlab-read-pcb-layout`
- Analyzing S-parameters, fields, or EM performance — use `matlab-analyze-em`
- Analyzing crosstalk between signal traces — use `matlab-design-pcb-transmission-line`
- Defining dielectric or conductor materials — use `matlab-manage-pcb-material`
- Modeling via structures — use `matlab-model-via`

## Typical Workflow

1. **Before:** `matlab-read-pcb-layout` — import the PCB layout from Gerber/ODB++/Allegro
2. **This skill:** Run DC analysis, check IR drop, evaluate design rules, batch-analyze nets
3. **After:** Iterate on the physical design in CAD and re-import, or use results to inform stackup changes via `matlab-manage-pcb-material`

## Quick Reference

| Task | Code |
|------|------|
| Import PCB layout | `pcb = pcbFileRead('board_native')` |
| List all nets | `netList = cadnetList(pcb)` |
| Find power nets | Filter `cadnetList(pcb)` with `regexpi` (see below) |
| Find specific rail | `idx = ~cellfun(@isempty, regexpi(netList.CadnetName, "P0V8"))` |
| Infer rail voltage | Parse net name with regex helper `parseNetVoltage` (see below) |
| Create cadnet | `cnet = cadnet(pcb, 'P0V8')` |
| Show cadnet layout | `show(cnet)` |
| Find components on net | `comps = findComponents(cnet)` |
| Filter by type | `inductors = findComponents(cnet, "ComponentType", "Inductor")` |
| Create PDN model | `PDN = powerDistributionNetwork(cnet)` |
| Assign topology | `setNetworkParameters(PDN, Source=src, Load=load, Sense=sense)` |
| Auto-assign topology | `setNetworkParameters(PDN, AutoAssignDefault='True')` |
| Set DC parameters | `setDCParameters(PDN, "NominalVoltage", 0.8, "LoadCurrent", 1)  % placeholder — ask user` |
| Set DC rules | `setDCRules(PDN, "MaxCurrentDensity", 0.5, "MinVoltage", 0.784)` |
| Voltage distribution | `voltage(PDN)` |
| Voltage with violations | `voltage(PDN, ShowViolation=true)` |
| Current distribution | `current(PDN)` |
| Current with arrows | `current(PDN, Direction='on')` |

## PCB Import and Net Discovery

### Importing a PCB Layout

`pcbFileRead` imports a PCB file and returns an object for hierarchical inspection. Supported formats: native directory (CSV files), ODB++ (zipped or unzipped), and Cadence Allegro `.brd` (requires one-time `extractaSetup()`).

```matlab
% Native format (directory containing CSV files)
pcb = pcbFileRead(fullfile(boardDir, 'pcie5_native'));

% ODB++ format
pcb = pcbFileRead(fullfile(boardDir, 'myboard.zip'));

% Allegro .brd (run extractaSetup() once first)
extractaSetup();  % one-time setup for Allegro support
pcb = pcbFileRead(fullfile(boardDir, 'myboard.brd'));
```

The returned object exposes: `NumLayers`, `NumCadnets`, `NumPadStacks`, `NumComponents`, `NumParts`, `LayerHeight`.

### Listing All Nets

```matlab
NetList = cadnetList(pcb);
disp(NetList);
```

Returns a table with columns: `CadnetIdx`, `CadnetName`, `NumPins`, `Length`. A real board may have 3000+ nets.

### Finding Power Nets

There is no built-in `findPowerNets` function. Filter the `cadnetList` output using regex to identify power and ground nets by name:

```matlab
netList = cadnetList(pcb);

% Define naming patterns (case-insensitive)
powerPatterns = ["^P\d+V", "^VDD", "^VCC", "^AVDD", "^DVDD", "^VDDO"];
groundPatterns = ["^GND", "^AGND", "^DGND", "^PGND", "^VSS", "^AVSS", "^DVSS"];

% Match power nets
isPower = false(height(netList), 1);
for p = powerPatterns
    isPower = isPower | ~cellfun(@isempty, regexpi(netList.CadnetName, p));
end
powerNets = sortrows(netList(isPower, :), 'NumPins', 'descend');

% Match ground nets
isGround = false(height(netList), 1);
for g = groundPatterns
    isGround = isGround | ~cellfun(@isempty, regexpi(netList.CadnetName, g));
end
groundNets = sortrows(netList(isGround, :), 'NumPins', 'descend');

% Filter by minimum pin count
minPins = 5;
powerNets = powerNets(powerNets.NumPins >= minPins, :);

% Search for a specific pattern (e.g., 0.8V rails)
idx = ~cellfun(@isempty, regexpi(powerNets.CadnetName, "P0V8"));
rails_0v8 = powerNets(idx, :);
```

**Common power net naming conventions (case-insensitive):**
- Power rails: `P<digit>V<digit>` (P0V8, P3V3_AUX, P12V), `VDD*`, `VCC*`, `AVDD*`, `DVDD*`, `VDDO*`
- Ground nets: `GND*`, `AGND*`, `DGND*`, `PGND*`, `VSS*`, `AVSS*`, `DVSS*`

### Inferring Rail Voltage from Net Name

There is no built-in `inferRailVoltage` function. Parse voltage from net names using regex:

```matlab
function nomV = parseNetVoltage(netName)
    netName = string(netName);
    % Pattern: P<int>V<frac> (e.g., P0V8 → 0.8, P3V3 → 3.3, P12V → 12.0)
    tok = regexp(netName, '(?i)P(\d+)V(\d*)', 'tokens');
    if ~isempty(tok)
        intPart = str2double(tok{1}{1});
        fracStr = tok{1}{2};
        if isempty(frac

SAFEgrade B · trust 89/100 Nothing in the source contradicts what it says it does. Grade A is reserved for packages that have also passed the behavioural sandbox.

What the source does

Filesystem

none-observed

Network

none-observed

Shell

none-observed

Dependencies

pinned

Secrets in source

none-found

Findings (0)

No findings outside the package's declared scope.

Gates applied: no_behavioural_pass.