Atlas / Skills / leoyeai / Rf Circuit Design

Rf Circuit DesignSAFE

skills/leoyeai/rf-circuit-design

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Verdict
SAFE
Grade
B
Trust score
89 /100
Version
—
Hosts
1 documented
License
MIT
Stars
2,160
01

Overview

🧠 Curated collection of 1209+ best OpenClaw skills — weekly updated by MyClaw.ai

Read from source at commit 4f3b4a2a472eOBSERVED · 2026-10-08
02

Host compatibility

What the documentation claims. We have not run a compatibility test.

HostStatusNotes
openclawmentioned
03

What it tells the agent

The instruction file, verbatim from the audited commit — this is the text the model reads, and the surface the audit's instruction layer examines. Quoted here so you can judge it without cloning anything.

---
name: "rf-circuit-design"
description: "提供射频电路设计与调试的专业指导。当用户询问射频电路原理图设计、PCB布局、阻抗匹配、调试技巧等问题时调用。"
---

# 射频电路设计与调试

## 一、射频电路设计基础

### 1.1 设计流程
```
需求分析 → 方案选择 → 器件选型 → 原理图设计 → PCB布局 → 仿真验证 → 样板制作 → 调试测试 → 问题排查 → 优化迭代 → 量产支持
```

### 1.2 关键设计原则
```
黄金法则:
1. 阻抗控制: 全程50Ω(或目标阻抗)
2. 最短路径: 射频走线尽可能短
3. 良好接地: 充足的接地过孔
4. 隔离设计: 输入输出充分隔离
5. 去耦完善: 电源去耦电容合理配置
```

### 1.3 常用频段参考

| 应用 | 频率范围 | 常用板材 | 特征阻抗 | 波长(空气) |
|------|---------|---------|---------|-----------|
| GPS L1 | 1575.42MHz | FR4/Rogers | 50Ω | 19.0cm |
| WiFi 2.4G | 2400-2500MHz | FR4 | 50Ω | 12.5cm |
| WiFi 5G | 5150-5850MHz | Rogers/Fastrak | 50Ω | 5.2cm |
| 5G Sub-6 (n78) | 3300-3800MHz | Rogers | 50Ω | 8.3cm |
| 5G Sub-6 (n79) | 4400-5000MHz | Rogers | 50Ω | 6.4cm |
| WiFi 6E | 5925-7125MHz | Rogers | 50Ω | 4.2cm |

## 二、原理图设计

### 2.1 射频链路设计

#### 接收链路设计
```
天线 → ESD保护 → 匹配网络 → 滤波器 → LNA → 级间放大 → 混频器/ADC

设计要点:
- LNA输入: 噪声匹配优先,而非功率匹配
- 第一级LNA: 决定整体NF,优化最关键
- 增益分配: 每级增益10-15dB,避免过载
- 滤波器位置: 放在LNA之前抑制干扰,或LNA之后减少插入损耗
```

#### 发射链路设计
```
DAC/基带 → 滤波器 → 调制器 → 驱动放大器 → PA → 滤波器 → 天线

设计要点:
- PA输入: 确保驱动电平达到P1dB
- PA输出: 负载线设计实现最大功率输出
- 谐波抑制: 输出滤波器抑制2/3次谐波
- 功率检测: 定向耦合器实现VSWR检测
```

### 2.2 阻抗匹配网络设计

#### L型匹配网络

**适用场景**: 简单匹配,Q值适中,频段宽度要求一般

```
拓扑结构:
        Ls
   ────/\/\/\────┬────
                ═══ Cp
                ─────
                 GND

设计公式:
Q = √(Rhigh/Rlow - 1)
Ls = Q × Rlow / ω
Cp = 1 / (Q × Rhigh × ω)

其中 ω = 2πf
```

**设计案例: 2.4GHz匹配**

```
目标: Zs = 100Ω → ZL = 50Ω, f = 2.45GHz

计算:
Rhigh = 100Ω, Rlow = 50Ω
Q = √(100/50 - 1) = √(2 - 1) = 1
ω = 2π × 2.45×109 = 1.54×1010 rad/s

Ls = Q × Rlow / ω = 1 × 50 / (1.54×1010) = 3.25nH
Cp = 1 / (Q × Rhigh × ω) = 1 / (1 × 100 × 1.54×1010) = 0.65pF

实际取标称值: Ls = 3.3nH, Cp = 0.6pF
```

#### π型匹配网络

**适用场景**: 需要阶跃阻抗变换,抑制谐波

```
拓扑结构:
    Cp1        Ls        Cp2
   ════───\/\/\/\/───╪═══
                      ─────
                       GND

设计步骤:
1. 选择带宽/品质因数Q
2. 计算中间阻抗: Rm = Rsource × Q2 或 Rload × Q2
3. 分两步设计两个L型网络

特点:
- π型具有低通特性,可抑制谐波
- 适合PA输出匹配
- Q值越高,带宽越窄
```

**设计案例: 5G PA输出匹配**

```
目标: Zs = 5+j10Ω (PA输出) → ZL = 50Ω, f = 3.5GHz

设计步骤:
1. 将PA阻抗转换为导纳: Ys = 1/(5+j10) = 0.08-j0.16 S
2. 选择Q=3获得适度带宽
3. 计算中间阻抗对应导纳: Gm = Q2/Rhigh = 9/50 = 0.18 S
4. 并联Cp1提供 susceptance 补偿
5. 串联Ls变换阻抗
6. 并联Cp2优化匹配

实际取值: Cp1 = 1.8pF, Ls = 2.2nH, Cp2 = 0.8pF
```

#### T型匹配网络

**适用场景**: 高阻抗变换比,需要灵活控制两端Q值

```
拓扑结构:
       Ls1           Ls2
   ──\/\/\/\──┬──\/\/\/\──
              ═══ Cp
              ─────
               GND

设计公式:
Q1 = √(Rsource/Rintermediate - 1)
Q2 = √(Rload/Rintermediate - 1)
Cp = 1 / (ω × Rintermediate × Q1)
Ls1 = Q1 × Rsource / ω
Ls2 = Q2 × Rload / ω
```

#### 史密斯圆图匹配方法

**基础操作原理**:
```
史密斯圆图结构:
- 水平直径: 纯电阻线 (左端R=0, 右端R=∞)
- 垂直直径: 纯电抗线 (上端X=+∞, 下端X=-∞)
- 中心点: Z = 50Ω (完美匹配点)
- 上半圆: 感性阻抗 (X>0)
- 下半圆: 容性阻抗 (X<0)

阻抗→归一化: z = Z/50Ω
```

**匹配移动规则**:
```
沿等电阻圆移动 (串联元件):
- 串联电感L: 沿等R圆顺时针移动 (X增加)
- 串联电容C: 沿等R圆逆时针移动 (X减少)

沿等电导圆移动 (并联元件):
- 并联电感L: 沿等G圆逆时针移动 (B增加)
- 并联电容C: 沿等G圆顺时针移动 (B减少)
```

**实战案例: 从Z=100+j50Ω匹配到50Ω**

```
步骤1: 归一化
z = 100/50 + j50/50 = 2 + j1

步骤2: 确定移动路径
- 当前点位于等R圆R=2的上方(感性区)
- 需要向中心点(1+j0)移动

步骤3: 选择串联电容(逆时针移动)
沿R=2圆向下移动,消去j1感抗
所需电容: Xc = -50Ω
C = 1/(ω×50) = 1/(2π×2.45G×50) = 1.3pF

步骤4: 验证
Z' = 100 - j50 + (-j50) = 100Ω
接近50Ω但还有倍数关系,需继续调整

步骤5: 并联电感匹配
在z'=2处并联电感
目标: 将R=2圆上的点移到R=1圆上
所需并联电感: L = 50/(ω×2) = 3.3nH
```

### 2.3 偏置电路设计

#### LNA偏置电路

**标准电路拓扑**:
```
              Vcc (2.7-5V)
               │
              ┌┴┐
              │ │ Rbias (偏置电阻)
              └┬┘
               ├─────────────────┐
               │                 │
              ┌┴┐              ┌┴┐
         Lchoke│ │         Cblk│ │ (隔直)
              └┬┘              └┬┘
               │                 │
              ┌┴┐              ┌┴┐
         Cdec1│ │              │ │ LNA
              └┬┘              ┤ │
               │                └┬┘
              GND               GND

去耦电容配置 (金字塔式):
Vcc → [10μF] → [100nF] → [10pF] → LNA_Vcc
```

**各频段电感选择参考**:
| 频段 | 推荐电感值 | 最低SRF要求 | 典型Q值 |
|------|-----------|------------|---------|
| GPS L1 (1.575GHz) | 22-47nH | 3GHz | >30 |
| WiFi 2.4G (2.45GHz) | 15-33nH | 5GHz | >35 |
| WiFi 5G (5.5GHz) | 8.2-15nH | 10GHz | >40 |
| 5G Sub-6 (3.5GHz) | 10-22nH | 7GHz | >35 |

**偏置电阻计算**:
```
公式: Rbias = (Vcc - Vds) / Id

示例:
Vcc = 3.3V, Vds = 2.5V, Id = 10mA
Rbias = (3.3 - 2.5) / 0.01 = 80Ω

常用值: 47Ω, 51Ω, 68Ω, 82Ω, 100Ω
```

#### PA偏置电路

**大电流供电设计**:
```
设计要点:
1. 电源线宽: 100mil/A (最小)
2. 去耦电容: 100μF + 10μF + 100nF + 10pF
3. 上电时序: Vcc先于Vctrl上电
4. 热设计: 温升<25°C

典型电路:
                    ┌──[100μF]──┐
                    │           │
VCC_PA ──┬──[10μF]──┴──[100nF]──┴──[10pF]── PA_Vcc
         │                                      │
        GND                                    GND
```

#### GPS LNA完整偏置设计案例

```
设计参数:
- 频率: 1575.42MHz
- 供电: 2.7V
- 电流: 5mA
- 目标NF: <1dB

电路设计:
VCC(2.7V) ──┬──[10μF, 0603]──┬──[100nF, 0402]──┬──[10pF, 0402]──┬── LNA_VCC
            │                 │                 │                │
           GND              GND              GND              GND

偏置电感:
- 型号: Murata LQG15HS27NJ02
- 电感值: 27nH
- SRF: 4.5GHz
- Q值: 35@1GHz

输入隔直电容:
- 型号: Murata GRM1555C1H220JA01
- 电容值: 22pF
- 耐压: 50V
- Q值: >200@1GHz

PCB布局要求:
- LNA输入走线<3mm
- 输入端下方完整地
- 所有GND过孔<100mil间距
```

### 2.4 射频开关电路设计

#### SPST/SPDT开关
```
典型电路 (SP4T):
         RFC
          │
    ┌─────┴─────┐
    │  MXD8641  │
    │           │
    ├─ RF1      │
    ├─ RF2      │
    ├─ RF3      │
    └─ RF4      │

控制逻辑:
V1 V2 | 导通端口
0  0  | RFC-RF1
0  1  | RFC-RF2
1  0  | RFC-RF3
1  1  | RFC-RF4

设计要点:
- 控制电压: 0V/2.8V (CMOS兼容)
- 上拉/下拉电阻: 10kΩ
- 布线: 控制线远离射频线
```

## 三、PCB布局设计

### 3.1 板材选择

| 板材类型 | 介电常数(εr) | 损耗角正切(tanδ) | 适用频段 | 成本 |
|---------|--------------|-----------------|---------|------|
| FR4 | 4.3 | 0.025 | <3GHz | 低 |
| Rogers RO4003C | 3.55 | 0.003 | 1-10GHz | 中 |
| Rogers RO4350B | 3.66 | 0.004 | 1-20GHz | 中 |
| Rogers RT/duroid 5880 | 2.2 | 0.0009 | 1-40GHz | 高 |
| Panasonic Megtron6 | 3.4 | 0.004 | 1-10GHz | 中高 |

### 3.2 层叠设计

#### 四层板设计
```
推荐层叠 (总厚度1.0mm):
┌────
04

Trust audit

SAFEgrade B · trust 89/100 Nothing in the source contradicts what it says it does. Grade A is reserved for packages that have also passed the behavioural sandbox.

LayerWhat it checksResult
L0Provenance & inventoryPASS
L1Static analysis of the codeWARN
L2Instruction surface (what it tells the agent)PASS
L3Class-specific surfacePASS
L4Behavioural (sandbox)SKIPPED

What the source does

Filesystem
none-observed
Network
none-observed
Shell
none-observed
Dependencies
pinned
Secrets in source
none-found

Findings (1)

MEDIUMObfuscation / stealth · obf.base64_blob · CWE-506, CWE-94
skills/compdf-conversion-cli/scripts/license.xml:9
<key>k5Ey9KFlkqpj+SDkUw+5ED9lTA3En/qUi0zdrydUCH3kMWTE3Eh65NXnFCaxlY2omY2JHnlEoK7Li7oOEvM7eG5VPdcO/sFlMfoCRdnLYdepJ+uLzYwOWR8W4yQVve/clxVFTVRL4DFleKInGdpAxIbHZT2yi4ADAMENls1N1XSLojRuqXePXDeAT/4Mv4TTx0s

Gates applied: no_behavioural_pass.

Audited 2026-10-08 · audit v0.4.1 · source sha 4f3b4a2a472efull audit observations/trust-audit/skill/leoyeai__rf-circuit-design.json · Report an issue / request a re-scan
05

Audit history

Every audit this skill has had.

DateSourceVerdictGradeScoreChange
2026-10-084f3b4a2a472eSAFEB89first audit
06

Questions

What does the Rf Circuit Design skill do?

🧠 Curated collection of 1209+ best OpenClaw skills — weekly updated by MyClaw.ai

Is Rf Circuit Design safe to install?

The audit found nothing in the source that contradicts what it says it does, and graded it B (89/100). Grade A is held back for packages that have also passed a sandboxed behavioural run, which is why a clean skill reads B.

What can Rf Circuit Design access on my machine?

The audit observed no filesystem, network or shell use at all in its source.

Which assistants does Rf Circuit Design work with?

Its documentation mentions openclaw. That is what the text claims, not a compatibility test we ran.

How current is this page?

The grade is for one exact copy of the source (4f3b4a2a472e), read on 2026-10-08. The repository is watched, and a new audit runs when it changes — this is the first audit.

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