Kicad

What the source does

• FilesystemDeclared1 observation
• NetworkDeclared10 observations
• ShellNone observedNo commands run in the source
• DependenciesPinnedNothing floats
• SecretsNone foundNo keys in source

Five audit layers

Gates applied: no behavioural pass.

.agents/skills/bom

.agents/skills/datasheets

.agents/skills/digikey

.agents/skills/element14

.agents/skills/emc

vrm_r_out = 0.05   # 50mΩ typical LDO output impedance

vrm_r_out = 0.1    # 100mΩ typical switching reg output impedance

f"(Rθ_JA={a['rtheta_ja_effective']:.0f}°C/W). "

f"(Rθ_JA={a['rtheta_ja_effective']:.0f}°C/W). "

lines.append(f"{'Ref':<8} {'Type':<14} {'P(W)':<8} {'Rθ_JA':<8} "

Audit 0.4.1 · source sha 4790730940af · 15 Oct 2026Report an issue or request a re-scan

• Publisheraklofas GitHub userOwner of the repository this skill is read from
• Source folderaklofas/kicad-happy/skills/kicadThe exact folder we audited
• LicenceMITAs the repository states it
• Commit pinned for this verdict4790730940afA new audit runs when the source changes
• Repository statusNot archivedPushed today
• Sandboxed runNot runSkills are read, not executed; layer L4 is skipped

Its description: Analyze KiCad projects and PDF schematics: schematics, PCB layouts, Gerbers, footprints, symbols, netlists, and design rules. Reviews designs for bugs, traces nets, cross-references schematic to PCB, extracts BOM data,…

---
name: kicad
description: >-
  Analyze KiCad projects and PDF schematics: schematics, PCB layouts, Gerbers,
  footprints, symbols, netlists, and design rules. Reviews designs for bugs,
  traces nets, cross-references schematic to PCB, extracts BOM data, checks
  DRC/ERC, DFM, power trees, and regulator circuits. Every finding carries a
  confidence label and evidence source with trust_summary rollup. Analyzes PDF
  schematics from dev boards, reference designs, eval kits, and datasheets.
  Supports KiCad 5–10. Use whenever the user mentions .kicad_sch, .kicad_pcb,
  .kicad_pro, PCB design review, schematic analysis, PDF schematics, reference
  designs, Gerber files, DRC/ERC, netlist issues, BOM extraction, signal
  tracing, power budget, DFM, or wants to understand, debug, compare, or
  review any hardware design. Also for "check my board", "review before fab",
  "what's wrong with my schematic", "is this ready to order", "check my power
  supply", "verify this circuit", OSHWA certification readiness, or any
  electronics/PCB design question.
---

# KiCad Project Analysis Skill

## Related Skills

| Skill | Purpose |
|-------|---------|
| `bom` | BOM extraction, enrichment, ordering, and export workflows |
| `digikey` | Search DigiKey for parts (prototype sourcing) |
| `mouser` | Search Mouser for parts (secondary prototype source) |
| `lcsc` | Search LCSC for parts (production sourcing, JLCPCB) |
| `element14` | Search Newark/Farnell/element14 (international sourcing, reliable datasheets) |
| `jlcpcb` | PCB fabrication & assembly ordering |
| `pcbway` | Alternative PCB fabrication & assembly |
| `spice` | SPICE simulation verification of detected subcircuits |
| `emc` | EMC pre-compliance risk analysis — consumes schematic + PCB analyzer output |

**Handoff guidance:** Use this skill to parse schematics/PCBs and extract structured data. Hand off to `bom` for BOM enrichment, pricing, and ordering. Hand off to `digikey`/`mouser`/`lcsc`/`element14` for part searches and datasheet fetching. Hand off to `jlcpcb`/`pcbway` for fabrication ordering and DFM rule validation. **Always run `spice`** for simulation verification during design reviews when any SPICE simulator is installed (check with `which ngspice ltspice xyce`). **Always run `emc`** for EMC pre-compliance risk analysis during design reviews when both schematic and PCB analysis are available. These are not optional — skipping them leaves value-computation errors and EMC risks undetected.

**Before analysis:** When the user asks to analyze or review a KiCad project, check whether a `datasheets/` directory exists in the project. If not, and DigiKey API keys are available (`DIGIKEY_CLIENT_ID`), offer to sync datasheets first: "I can download datasheets for your components before analysis — this enables pin-level verification and decoupling validation against manufacturer specs. Want me to sync them?" If the user declines or no API keys are set, proceed without datasheets — the analysis works without them but datasheet verification findings won't be available.

**If you see a `DS-001` finding in the analyzer output** (severity `high`, detector `audit_datasheet_coverage`), the review cannot make any verified claim. Stop and either (a) run the datasheet sync via `digikey` / `mouser` / `lcsc` / `element14` (whichever has credentials/stock), (b) populate MPNs on the BOM parts, or (c) state explicitly in the report that every pin-level, electrical, and regulator finding is *consistency only* — do not use the words "verified", "confirmed", or "per datasheet" anywhere. `DS-002` (datasheets missing but MPNs set) and `DS-003` (partial MPN coverage) are softer variants with the same implication for the parts they cite.

## Design Review Contract

When the user asks for a **design review**, **complete report**, **ready-to-fab assessment**, or anything equivalent, do not stop at running one or two analyzers and summarizing their findings. A design review in this skill has a stricter contract:

1. Read the full workflow in this `SKILL.md`, not just the analyzer command sections.
2. Read `references/report-generation.md` before writing the report.
3. Run every applicable analyzer for the files present in the project, then say explicitly which ones were and were not run.
4. Perform raw-file and datasheet cross-verification before claiming anything is "verified".
5. Triage likely analyzer false positives before elevating them into blockers.
6. If a required step could not be done, state it as a review gap, not as silent omission.

Treat this as the minimum bar. Analyzer JSON alone is not the final review.

### Minimum Review Checklist

For a full design review, explicitly account for each item below in the report:

- `datasheets/` present, synced, or verification gap stated
- `analyze_schematic.py`
- `analyze_pcb.py --full`
- `cross_analysis.py`
- `analyze_emc.py`
- SPICE simulation when any simulator is installed
- `analyze_thermal.py` when both schematic and PCB JSON exist
- `analyze_gerbers.py` when fabrication outputs exist
- lifecycle audit when network access and MPN coverage allow it
- prior review / prior run delta check
- raw schematic/PCB spot-verification elevated to full verification for critical parts
- explicit report sections for blockers, verification basis, false positives, and skipped analyses

If an item is not applicable, say why. If it was skipped, say why. If it failed, say how that limits confidence.

### Common Review Failure Modes

These are the failure modes this contract is meant to prevent:

- Stopping after schematic + PCB + EMC output and calling it a complete review
- Reporting analyzer findings without checking whether they are expected layout artifacts
- Claiming "verified" without direct datasheet evidence or structured extraction evidence
- Omitting thermal, lifecycle, prior-review delta, or gerber checks without disclosure
- Writing a report that lacks a verdict, blockers table, verification basis, or skipped-analy

Excerpt, first 6,000 characters of SKILL.md, verbatim from the audited commit. It is text from someone else’s repository, quoted so you can judge it before your agent reads it.

1. 2026-10-15
   !CAUTION B 85 / 100

   first audit · source 4790730940af

Questions about Kicad

• github.com/aklofas/kicad-happy/tree/main/skills/kicad — the audited source at commit 4790730940af and every finding aboveObserved · 15 Oct 2026

Spotted something wrong? Report a correction · Methodology